1. Field of the Invention
This invention relates to a bipolar transistor formed in a slot. More particularly, this invention relates to formation of a bipolar transistor having its active regions formed in slots in an integrated circuit substrate.
2. Discussion of the Related Art
The density of integrated circuits continues to increase. Advances in lithography have permitted line width resolution to reach micron dimensions and processing techniques have improved to the point where the reliable formation of thin films and precise etching are both possible so that smaller and more predictable feature sizes can be obtained. As a consequence, the lateral dimensions of devices are reaching micron levels and passing on into nanometer ranges resulting in a continued decrease in the density of integrated circuits.
Thus, a greater number of individual devices can be fabricated in a given area. While further increases in areal density are likely, physical, equipment, and process limits are being approached. In addition, as devices become smaller and smaller, their power ratings are reduced and the relative importance of problems such as parasitic capacitance and contamination is increased. Due to the diminishing return to be obtained from further efforts to improve areal density, it has become desirable to consider the possibility of increasing the extent of the active regions in the vertical dimension to thereby obtain performance for a device with established lateral dimensions which is equivalent to the performance of a device with greater lateral dimensions. Also higher power or higher performance devices may be obtained in this way.
Bipolar transistors typically have a vertical structure as shown, for example in Horng et al U.S. Pat. No. 4,392,149 which relates to a method for formation of a bipolar transistor having an oxide spacer between the emitter and the external base region which permits very close spacing therebetween. A buried collector layer is provided which is connected to a collector contact by a well or reach through.
Ohuchi et al U.S. Pat. No. 4,302,763 describes a semiconductor device which includes a semiconductor substrate with a first region of first conductivity type in the substrate which apparently comprises the collector. A second region of a second conductivity type is also formed in the substrate adjacent to the first region and presumably forms the base of the transistor. A third region of the first conductivity type, which apparently includes the emitter, is formed adjacent to the second region and includes at least a portion on the substrate which is comprised of the same element as the substrate and oxygen. The band gap energy of this portion is said to be larger than that of the second region. A SIPOS layer is used to form the emitter by diffusion of the impurities of the SIPOS layer into the underlying base region.
As the densities of integrated circuits have increased, there has been serious consideration of using trench or slot formation processes for forming the insulating zones between individual transistors. See, e.g., D. N. K. Wang et al, "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 3, 1983, pp. 157, 159 (157-159?). In theory, slot isolation would allow individual devices to be packed closer together. Such an isolation technique is described in Bondur et al U.S. Pat. No. 4,104,086 as well as in Bonn U.S. Pat. Ser. No. 719,085 and Gwozdz U.S. patent application Ser. No. 759,621, both of which applications are assigned to the assignee of this application. Bower U.S. Pat. No. 4,533,430 describes and claims a process for forming such slots having near vertical sidewalls at their upper extremities to avoid formation of voids when refilling the slot.
Bondur et al U.S. Pat. No. 4,139,442 discloses the formation of a deeply recessed oxidized region in silicon by forming a series of closely spaced trenches and then oxidizing the walls of the trenches to utilize all of the remaining silicon comprising the walls of adjoining trenches. Lillja et al, in an article entitled "Process For Fabrication Of Shallow and Deep Silicon Dioxide Filled Trenches", published in IBM Technical Disclosure Bulletin, Vol. 22, No. 11 in April, 1980, describes the process steps involved in forming a bipolar transistor in an integrated circuit structure using isolation oxide materials which comprises forming a shallow oxide trench to separate the base and collector contact regions and a deeper oxide filled trench which surrounds the entire transistor.
Takemoto et al U.S. Pat. No. 4,484,211 teaches a bipolar transistor structure with an oxide isolation between the emitter and and the extrinsic base so that the capacitance between the emitter and the base is lowered.
Horng et al U.S. Pat. No. 4,339,767 discloses a process for forming a vertical NPN transistor and a lateral PNP transistor at the same time on a substrate with deep oxide-filled trenches electrically isolating the devices from one another. To eliminate the emitter current ejecting into the substrate, the P+ emitter and the P+ collector of the lateral PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
In addition to forming slots in semiconductor wafers for isolating individual devices, slots have also been considered for use as passive circuit elements. For example, it has been proposed that a slot be filled with an appropriate material so that it will function as a capacitor. See, e.g., K. Minegishi et al., "A Sub-Micron CMOS Megabit Level Dynamic RAM Technology Using a Doped Face Trench Capacitor Cell", Proceedings, IEDM, 1983, p. 319; and T. Morie et al., "Depletion Trench Capacitor Technology for Megabit Level MOSdRAM", IEEE Electron Device Letters, v. EDL-4, No. 11, p. 411, Nov. 1983. Such applications are possible because with appropriate filling materials a slot can be made to be conductive or insulating as required.
It has also been proposed to construct active devices in slots in a substrate. Fujitsu Japanese Patent Document No. 57-11150 discloses construction of a lateral bipolar transistor wherein an emitter region is formed in a substrate by diffusing impurities into the substrate through the walls of a first slot formed in the substrate. A collector region is similarly formed in the substrate using a second slot formed in the substrate, located adjacent the first slot, to diffuse impurities into the substrate. The portion of the substrate between the emitter region and the collector region in the substrate is said to form the base of the transistor.
Engeler et al U.S. Pat. No. 3,762,966 teaches the formation of a bipolar transistor with precise control over width of the base region. The transistor is formed by first growing an N-type doped epitaxial layer over a heavily doped N-type semiconductor wafer to form a collector layer and then diffusing a heavily doped P-type base contact region into the epi layer. The structure is then masked with an oxide layer through which one or more openings or holes are etched through the base contact region into the N-type collector layer to permit formation of one or more emitters. Strongly N-type semiconductor material, containing both N-type impurities and faster diffusing P-type impurities, is then epitaxially grown to fill the holes. The structure is then heated to form an active base region below the emitter by diffusion into the epi collector layer of acceptor impurities from the doped epitaxial emitter material. The active base region is in contact with the epitaxial base contact region adjacent the emitter region. Metal contact are then formed to the epitaxial collector layer, the emitter, and the base contact region to complete the transistor.
Vora U.S. Pat. No. 3,703,420 discloses various methods for constructing lateral transistors in integrated circuit structures, respectively using monocrystalline and polycrystalline silicon which comprises forming a first epitaxial layer over a substrate and then doping an upper portion of this layer to form a base contact region therein. In the polycrystalline method, silicon oxide islands are formed on the epi layer and a second layer of epitaxial silicon is grown over the first layer. The second epitaxial layer is monocrystalline above the substrate and polycrystalline above the silicon dioxide. The structure is then masked to form openings in registry with the polysilicon portions and doped to form the active elements of the lateral transistor. The so-formed polycrystalline portions are used to convey dopant laterally into the adjacent monocrystalline portions to form the respective active elements of the lateral transistor. In both the monocrystalline and polycrystalline embodiments, the base and emitter are formed by doping through the same opening in the mask to form lateral P-N junctions between the base and emitter in the monocrystalline silicon. The base contact region in the first epi layer connects the base with a base electrode.